1. Field of the Invention
The present invention generally relates to relay boards and semiconductor devices having the relay boards, and more specifically, to a relay board provided in a semiconductor device having a structure where plural semiconductor chips are received in a single semiconductor package, for example, the relay board used for wiring the semiconductor chips or the semiconductor chip and a lead frame of the semiconductor package, and the semiconductor device having the relay board.
2. Description of the Related Art
It is well known to make a single package wherein plural chips having different functions are provided in a semiconductor package by using SiP (System in Package) technology. In a case where the plural semiconductor chips are provided in the single semiconductor package by using such a technology, it is necessary to wire-bond the semiconductor chips per se directly or wire-bond the individual semiconductor chips and the lead frame of the semiconductor package.
FIG. 1 is a plan view showing a related art semiconductor device using the SiP technology. Referring to FIG. 1, in a related art semiconductor device 10, a first semiconductor chip 11 is provided on a lead frame having bonding pads 19. A second semiconductor chip 18 is stuck and fixed on the first semiconductor chip 11. Four bonding pads 12-1 through 12-4 of the second semiconductor chip 18 are respectively connected to bonding pads 9-1 through 9-4 among bonding pads 9 provided at four sides of the first semiconductor chip 11. The bonding pad 9 of the first semiconductor chip 11 is connected to the bonding pad 19 of the lead frame by a bonding wire 17 for the lead frame.
However, in a case where plural semiconductor chips 11 and 18 are stuck together as in this case, the bonding wires such as bonding wires 13 and 14 for the first semiconductor chip 11 are overlapped, and wire lengths of the wires such as bonding wires 15 and 16 for the first semiconductor chip 11 are too long.
In order to solve such problems, as shown in FIG. 2 and FIG. 3, examples where a terminal chip for relaying a wiring by the bonding wire is provided in the semiconductor package are suggested.
FIG. 2 is a plan view of a first example of the related art semiconductor device where a terminal chip is provided. Referring to FIG. 2, in a semiconductor device 20, a terminal chip 25 is put between the first semiconductor chip 11 and the second semiconductor chip 18. Eight bonding pads 26 are formed in the terminal chip 25. In addition, four metal wirings 27 each connecting two bonding pads 26 are provided in the terminal chip 25. For example, one connected pair of the bonding pads 26 is connected to the bonding pad 12 of the second semiconductor chip 18 via the first bonding wire 24, the bonding pad 9 of the first semiconductor chip 11 via the first bonding wire 28, and the bonding pad 19 of the lead frame via the third bonding wire 29. Under this structure, the terminal chip 25 relays through the bonding wires 24, 28 and 29 so that the wire lengths may be shortened more than in the structure shown in FIG. 1.
FIG. 3 is a plan view of a second example of the related art semiconductor device where the terminal chip is provided. Referring to FIG. 3, in a semiconductor device 30, the second semiconductor chip 18 and a terminal chip 35 are provided on the first semiconductor chip 11 side by side. Six bonding pads 36 are formed in the terminal chip 35. Furthermore, three metal wirings 37 connecting two bonding pads 36 are provided in the terminal chip 35. Among the bonding pads 36 to which metal wirings 37 at a left side and in the middle of the terminal chip 35 are connected in FIG. 3, a bonding pad 36-1 is connected to the bonding pad 12 of the second semiconductor chip 18 via the first bonding wire 38. A bonding pad 36-2 is connected to the bonding pad 9 of the first semiconductor chip 11 via the second bonding wire 39 and further connected to the bonding pad 19 of the lead frame via the bonding wire 17 for the lead frame. Under this structure, the terminal chip 35 relays through the bonding wires 38 and 39 so that the overlapping of the bonding wires as in the structure shown in FIG. 1 is avoided. See Japan Laid-Open Patent Application Publications No. 61-112346, No. 8-78467, No. 2001-7278, and No. 2004-56023.
However, a size of the semiconductor chip being relayed for the terminal chip and the number or arrangement of the bonding pads formed in the semiconductor chip are varied. Therefore, even if a terminal chip is proper for the design of a certain semiconductor package, the terminal chip may not be always proper for the design of other semiconductor packages. That is, the terminal chips 25 and 35 shown in FIG. 2 and FIG. 3 may not always be proper for combination with semiconductor chips other than the semiconductor chips shown in FIG. 2 and FIG. 3.
Therefore, in the related art, it is necessary to manufacture and prepare a terminal chip for every design of or combination with one semiconductor chip mounted on another semiconductor chip.
The terminal chip which can be used for only a specific combination of the mounted semiconductor chip requires a long developing term and a high manufacturing cost.